1. Field of the Invention
The present invention generally relates to phase-change memory devices and methods for writing phase-change memory cells. More particularly, the present invention relates to phase-change memory devices and methods of writing phase-change memory devices in which write current pulse characteristics are varied according to a load of a phase-change cell to be written.
2. Description of the Related Art
Phase change memory cell devices rely on phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The differing resistance values exhibited by the two phases are used to distinguish logic values of the memory cells. That is, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.
FIG. 1 illustrates a phase-change memory cell in an amorphous state 52-1 and in a crystalline state 52-2. The phase-change memory cell may be part of a Phase-change Random Access Memory (PRAM). The phase-change memory cell 52 includes a phase-change layer 55 between a bottom electrode (BE) 54 and an upper electrode (UE) 56. The phase-change layer 55 is formed of a phase-change material, such as a chalcogenide alloy (GST). A bit line (BL) is coupled to the upper electrode 56. The bottom electrode 54 is coupled to ground through transistor NT. A word line (WL) is coupled to the gate of transistor NT.
When phase-change memory cell 52 is in an amorphous state 52-1, a portion of the phase-change layer 55 is amorphous. Likewise, when phase-change memory cell 52 is in a crystalline state 52-2, the portion of the phase-change layer 55 is crystalline. As shown by the equivalent circuit diagram in FIG. 1, the phase-change material layer 55 is SET (ST1) to the crystalline state or RESET (ST2) to the amorphous state depending on an electrical current applied via the bit line BL.
As would be appreciated by one skilled in the art, the terms “amorphous state” and “crystalline state” are not absolute characterizations of the phase-change material. Rather, when a portion of the phase-change material is said to be in an amorphous state (i.e. a RESET state), this means that the material is sufficiently amorphous to take on a resistive value R1 which may be readily distinguished from a resistive value R2 of the material in the crystalline state (SET state).
Conversely, when a portion of the phase-change material is said to be in a crystalline state (SET state), this means that the material is sufficiently crystalline to take on a resistive value which may be readily distinguished from the resistive value of the material in the amorphous state (RESET state).
FIG. 2 illustrates the temperature characteristics of a phase-change memory cell in a set programming operation and a reset programming operation. A set programming operation causes a phase-change material layer of a phase-change memory cell to crystallize, thus decreasing the resistivity of the phase-change material layer. Likewise, a reset programming operation causes a phase-change material layer of a phase-change memory cell to become amorphous, thus increasing the resistivity of the phase-change material layer.
As illustrated in FIG. 2, the programming of a phase-change memory cell is dependent on the temperature of the phase-change memory cell. An amorphizing (RESET) temperature pulse includes a rising portion 12, a peak portion 10, and a declining portion 14. In order to reset a phase-change memory cell, using an amorphizing (RESET) pulse, the phase change material layer is heated above its melting point (Tm) by a resistive heater for a relatively short period of time. Between time T0 and time T1, the temperature of the phase-change material layer is rapidly increased to a temperature above the melting point (Tm) of the phase-change material layer. During the declining portion 14, the phase-change material layer is rapidly cooled, thus causing the phase-change material layer to become relatively amorphous. In other words, raising the temperature of the phase-change material layer above its melting point (Tm) causes crystal structures in the phase-change material to be broken apart. Because the phase-change material layer is cooled rapidly, there is little opportunity for crystals to form in the phase-change material layer before the phase-change material layer becomes solid in a relatively amorphous state.
Likewise, a crystallizing (SET) temperature pulse includes a rising portion 22, a peak portion 20, and a declining portion 24. In order to set a phase-change memory cell, using a crystallizing (SET) pulse, the phase change material layer is heated above its crystallization point (Tx) by a resistive heater for a relatively short period of time (e.g. 50 ns), which is longer than the period of time that the temperature is raised during a amorphizing (RESET) temperature pulse. Between time T0 and time T2, the temperature of the phase-change material layer is rapidly increased to above the crystallization point (Tx) of the phase-change material layer and crystallization occurs. During the declining portion 24, the phase-change material layer is rapidly cooled, thus causing the phase-change material layer to set in a relatively crystalline state.
FIG. 3 comparatively illustrates the RESET current pulse G1 and the SET current pulse G2. The RESET current pulse G1, which is a relatively short pulse of magnitude I-RESET, causes the temperature of the phase-change material to RESET the material into an amorphous state as shown above in FIG. 2. The SET current pulse G2, which is a relatively long pulse of magnitude I-SET (where I-SET is less than I-RESET), causes the temperature of the phase-change material to SET the material into crystalline state as shown above in FIG. 2.
FIG. 4 illustrates a memory 100 having a phase-change memory cell array 160. As shown, the cell array 160 includes a plurality of memory blocks, namely, Block(A00) 160a, Block(A01) 160b, Block(A10) 160c, and Block (A11) 60d. Each memory block includes a plurality phase-change memory cells commonly connected to a word lines WLi, WLj, WLk, and WLl respectively contained in the memory blocks.
Buffers 110_1 and 110_2 receive addressing signals A0 and A1. The address signals A0 and A1 are decoded by a pre-decoder 120 to generate decoded signals A00_DEC, A01_DEC, A10_DEC, and A11_DEC, which in turn are decoded by a main decoder 140 to output block selection signals A00, A01, A10 and A11. The block selection signals A00, A01, A10 and A11 drive word lines WLi, WLj, WLk, and WLl of memory blocks 160a, 160b, 160c, and 160d, respectively.
A write driver 130 outputs a SET or RESET write current pulse SDL according to a programming signal SET(RESET)_CON_PULSE and a data signal DIN from buffer 111. A column decoder 150 then supplies the write current pulse SDL to the memory blocks 160a, 160b, 160c, and 160d. 
As illustrated in example FIG. 4, memory block 160d is closer to decoder 150 than memory cell block 160a. Accordingly, different loads are present from decoder 150 to the memory blocks 160a, 160b, 160c, and 160d. These loads are represented in the figure by resistive elements R1, R2, R3 and R4.
The differing loads of the memory blocks 160a, 160b, 160c, and 160d, result in different write conditions of the phase change memory cells of the memory blocks. This is explained with reference to FIGS. 5 through 7.
FIG. 5 is a simplified diagram illustrating the different set programming pulses (e.g. SET_CON_PULSE) applied to the phase-change memory cell blocks 160a, 160b, 160c, and 160d of the memory array 160. As can be seen from FIG. 5, the set programming pulses all have the same pulse width.
FIG. 6 illustrates the RESET resistance distribution regions of the phase-change memory cells in blocks 160a, 160b, 160c, and 160d. As the load of the memory blocks is increased, the resistance distribution region is decreased. In order to avoid write errors, the RESET write current pulse must be capable of writing the highest-load memory block 160a such that the lowest resistance distribution region (Region (A00)) is fully in a RESET region. Since the memory block 160d has the lowest load, a relatively strong RESET write current pulse is applied to memory cells of the memory block 160d. As such, a relatively high crystalline state is achieved which results in a relatively high resistance distribution region (Region (A11)). Conversely, the memory block 160a with the greatest load will exhibit a relatively low resistance distribution region (Region (A00).
FIG. 7 illustrates the SET resistance distribution regions of the phase-change memory cells in blocks 160a, 160b, 160c, and 160d. Again, as the load of the memory blocks is increased, the resistance distribution region is decreased. In order to avoid write errors, the SET write current pulse must be capable of writing the lowest-load memory block 160d such that the highest resistance distribution region (Region (A11)) is fully in a SET region. Otherwise, SET failures will occur in the portion WIN of the distribution region of the nearest block (Region (A11). Thus, in order to bring the Region (A11) fully into the SET region, the phase-change memory cells of the Region (A00) become “over-programmed”. That is, power is unnecessarily expended with regards to the SET programming of the phase-change memory cells associated with Region (A00). Further, additional power is needed to bring the same memory cells back into the RESET region during RESET programming.